Quantum
computing
Building the computer of the future
Quantum computers have the potential to perform extremely complex calculations, by encoding information into quantum states. This opens the way for revolutionary applications, such as complex optimisation challenges or prediction, simulation, and modelling of the behaviour of molecules, catalysts, and new materials.
Realising the promise of quantum computing requires the development of different layers of hardware and software. Together, these layers are referred to as the quantum computing stack. This stack is what we explore at QuTech. The base of the stack – the ‘quantum processor’ – contains the qubits. We are investigating different types of qubits, along with the system architecture that translates quantum algorithms into electronic signals that operate on the qubits.

Spin qubits
Long-term goal:
To build a modular spin-qubit processor for scalable quantum information processing.
Highlights
We observed iSWAP oscillations between two electron spins separated by about 250 micron, about three orders of magnitude longer than the typical separation between electron spins coupled by the exchange interaction. The interaction between the remote spins is mediated by virtual photons in an on-chip superconducting resonator. The oscillations are fast, with a period of about 100 ns, but also decayed quickly, within a few periods. Future devices with optimised charge noise could leverage this method to connect qubits over large distance on the chip, or even between chips.
We introduced and demonstrated a method for controlling spin qubits without barrier gates. By symmetrically pulsing the plunger gates, we realized two-qubit gates at the charge-symmetry point. This approach may significantly simplify scaling to large arrays, as it reduces heavily the number of control lines.
We used germanium spin qubits in micron-scale devices as sensitive probes to measure the noise levels in next generation germanium material stacks. We found a significant reduction when transitioning the epitaxy from a silicon to a germanium starting substrate. Our work demonstrates that this new material platform may lead to better and more uniform qubit performance, offering a promising path towards scalable quantum devices.
We demonstrated that single-electron spin qubits can be coherently controlled with high-fidelity (99.5%) using baseband pulses only. This work is directly inspired by previous work from us obtained last year on Ge hole spins. The latter relied on dot-do-dot variations of the local g-tensor. For silicon spin qubits, we instead engineered variations in the local magnetic field orientation by micromagnets. Compared to the conventional methods relying on microwave control signals, this baseband control method promises to exhibit reduced cross-talk and heating.
We demonstrated a 10-qubit array in germanium. We realized a two-dimensional array of quantum dots and showed that qubits can be controlled well above 99%. We studied the hole occupancy and driving efficiency and showed 3-hole operation together with plunger-gate driving can significantly reduce crosstalk.
We achieved universal control of four singlet-triplet qubits in a 4x2 Ge quantum dot array. Each pair of spins thereby encoded a single qubit, which could be controlled with >99.5% fidelity. By swapping the state of adjacent qubits, entanglement between neighbours could be distributed along the array, such that the first and last qubit in the chain became entangled.
We reported that a single electron spin can be shuttled back and forth over a cumulative distance of 10 micron in under 200 ns while preserving the spin state with a fidelity of 99.5%. The prospect that electron spin qubits can be transported fast and reliably over many microns encourages us to further explore architectures whereby spins are moved around both between and within quantum dot arrays.
We tracked the variation of the qubit frequency in a linear array of Si/SiGe quantum dots over the course of 912 days. Previous work had shown that the qubit frequency is the parameter that needs the most frequent recalibration. Studies over such time spans are rare, for obvious reasons, but ultimately very important for understanding the long-term stability of spin qubit devices and the qubit frequency.
Semiconductor-based quantum devices are often characterized in terms of the charge states of many quantum dots. To enable data-driven research into such devices, we have developed an open-source software package to efficiently simulate large arrays of quantum dots in arbitrary geometries.
Developed geometric optimal control framework for high-fidelity adiabatic state transfer for readout.

Transmon qubits
Long-term goal:
To realise an error-protected logical qubit with a superconducting circuit and a flexible control stack that also enables NISQ applications.
Highlights
We completed an investigation (ArXiv) of the optimal frequency positioning of tunable couplers to mitigate the impact of spectator qubits on all quantum operations (single-qubit gates, two-qubit gates, and readout). This investigation used a 5-qubit, 4 coupler prototype of our tunable-coupler device architecture. This architecture was scaled to 9- and 17-qubit processors throughout 2025.
We proposed and realised (ArXiv) a hardware-efficient leakage reduction unit (LRU) built into qubit readout and without any inherent time cost. Further, we demonstrated the usefulness of this LRU through improved quantum error correction in both memory and stability experiments, without any leakage post-selection. The poster on this work was co-recipient of the poster award at SQA 2025.
We completed an investigation (ArXiv) of qubit error bursts caused by ionising radiation on two superconducting quantum processors of Quantum Inspire. We identified and studied two effects, quasiparticle pumping and anomalous time dependence, that can respectively reduce the duration and frequency of such bursts.
Throughout 2025, we publicly released three new superconducting backends in the Quantum Inspire platform: Starmon-7, Tuna-5 and Tuna-9. The Tuna systems embody the open-architecture full-stack quantum computers that we integrate in collaboration with TNO and 4 companies in our quantum ecosystem (Orange Quantum Systems, Qblox, Delft Circuits, and QuantWare).

Cryogenic electronics
Long-term goal:
To replace room-temperature electronics that control quantum processors with integrated cryogenic electronics, operating in close proximity to the qubits, in order to facilitate large-scale quantum computers.
Highlights
We demonstrated the complete cryo-CMOS infrastructure required to voltage bias the electrodes of a large quantum-dot array. Consisting of a digital-to-analog converter in combination with a set of multiplexers, the proposed system can accurately bias up to 96 electrodes while operating below 70 mK thanks to the ultra-low-power dissipation of 1.2 µW per channel. (IEEE Transactions on Quantum Engineering)
We introduced a new framework to assess the impact of the non-idealities of adiabatic pulses on the fidelity of two-qubit gates in single-spin semiconductor qubits, thus allowing for an advanced optimisation of the electronics generating such pulses. Thanks to the insights deriving from this framework, we devised a novel technique, Delayed Leakage Reduction (DLR), that suppresses leakage at targeted frequencies for baseband control to enable fast high-fidelity operations. (ArXiv)
We derived extensive guidelines for the design of an integrated DC-readout interface for semiconductor spin qubits through a thorough analytical modelling of Single-Electron Transistor (SET) readout interfaces, thus identifying promising candidates for the cryogenic implementation of those readout, including solutions based on transconductance amplifiers and charge-integration front-ends. (IEEE Transactions on Circuits and Systems—I: Regular Papers)
We demonstrated a scalable cryo-CMOS readout solution for Superconducting Nanowire Single-Photon Detectors (SNSPDs) tailored for the readout of color-center-based qubits. The proposed system demonstrates competitive performance at 0.1 K, featuring low jitter, high speed and low dark count rate (<1Hz), while dissipating only 20 μW and occupying a silicon area of only 0.14 mm2 per SNSPD channel. Such ultra-low power and a compact footprint enable readout integration within a large-scale color-center quantum computer. (IEEE European Solid-State Electronics Research Conference (ESSERC)

Quantum computing architecture stack
Long-term goals:
To develop a scalable quantum computing control system stack that bridges the gap between quantum applications and quantum devices.
Highlights
We introduced ML4QGST, a Transformer-based approach to quantum gate set tomography that learns gate and noise parameters directly from experimental data, thus avoiding the usual computationally heavy iterative fitting loops. We used data grouping and curriculum learning to show that the model reliably recovers physically relevant noise parameters (such as coherent over-rotations and depolarising noise) with accuracy comparable to established GST pipelines. (Quantum Machine Intelligence)
We developed a pre-fabrication benchmarking framework for bilinear spin-qubit arrays that evaluates candidate architectures by their ability to generate genuine multipartite entanglement, complemented with circuit-level fidelity measures. Compilation-aware simulations under realistic noise, including crosstalk, showed that the expected gains from increased local connectivity can be negated by crosstalk, which provides guidance for hardware and compilation co-design. (PRX Quantum)
We introduced an energy-aware perspective on quantum optimal control by defining an explicit energetic cost for pulse-shaped gate implementations and deriving its gradient, so energy can be optimized directly alongside process fidelity. We then explored two complementary optimization strategies, an open-loop gradient method and a closed-loop learning approach driven by measurement feedback, and quantified the resulting fidelity-energy trade-offs under realistic noise. (Advanced Quantum Technologies)
We proposed a real-time QEC decoder based on hyperdimensional computing that maps syndrome streams to corrections using simple, highly parallel operations (bitwise logic and lightweight accumulations) with constant, syndrome-independent latency. The approach is designed explicitly for efficient implementation in hardware near the cryostat, with most complexity moved offline into the hypervector construction. (IEEE QCE)

Theory for assessing the performance of quantum processors employing superconducting and spin qubits
Long-term goal:
To provide analyses and ideas towards implementing and assessing the performance of quantum error correction for superconducting and spin qubits.
Highlights
Contribute to the understanding of measured anisotropies of exchange interactions in Ge hole qubits. (Nature Communications)
Predicted novel type of interactions in hole spins that can help speed up direct three qubit gates. (PRX Quantum)
Provided a theory for designing and utilising zero-g- factor spin qubits with baseband control. (Physical Review Letters)
We wrote a vision paper, outlining joint benefits between quantum computing and the field of data management. One such topic is speeding up classical simulation of quantum circuits, which is indispensible for performance assessment and design of (noisy) quantum chips. (VLDB Conference)
We showed how the popular family of bivariate bicycle (BB) codes can be realized with lower connectivity between the qubits without taking any hit in performance and we developed a general framework of morphing QEC circuits which is applicable to many more codes. (Physical Review Letters)
Verifying the performance of quantum computers is highly important, and this task often relies on standard benchmarking techniques. We wrote a hands-on tutorial on the most common technique called randomized benchmarking. (SciPost Physics Lecture Notes)
Furthermore, to assess the quantum resources required to describe quantum states, we developed theory and simulations to describe how quantum different quantum and classical algorithms are. (Machine Learning: Science and Technology)

Quantum Inspire: the multi hardware quantum technology platform
Long-term goals:
To develop a full-stack quantum computer demonstrator for training and education, along with co-development and collaborative R&D of quantum technologies for quantum computing.
Highlights
In 2025, great progress was made with important contributions by the hardware and software teams of Quantum Inspire, QuTech ‘s cloud-based multi-technology quantum computer for public use. Exciting developments in 2025 include the launch of Quantum Inspire 2.0. In more detail, Quantum Inspire 2.0 introduces a multitude of software improvements, from top to bottom. The website interface offers an enhanced user experience, while the new and improved cloud platform equips users with new quantum compilers and support for Qiskit and PennyLane, both widely used in the community. Improvements like these facilitate easy connections to other hardware and software platforms. Under the hood, significant software enhancements have been implemented. An important one is that Quantum Inspire 2.0 now has a built-in functionality that users can use to integrate quantum and classical computing, using a supercomputer node provided by SURF and co-located classical CPU.
Superconducting backend
- Validated tunable-coupler architecture at scale (Tuna-9): The tunable-coupler CZ scheme previously demonstrated on Tuna-5 was successfully scaled to Tuna-9 and released publicly. This confirms QEC-relevant architectural transferability.
- System integration maturity (1 week from cryo to cloud): Consolidated calibration, control, and cloud integration workflows enabled Tuna-9 to be placed online within 1 week after cryogenic characterisation. This demonstrates maturity of the full stack and sets a solid foundation for a repeatable open-architecture system integration expertise in Delft.
- Strategic mitigation for quantum processors: In-house fabrication and a structured collaboration with PeakQuantum were initiated alongside QuantWare iterations. This multi-path strategy strengthens the foundations of a resilient European quantum hardware supply chain, especially in light of Delft pitch for a central role as system integrator in the upcoming specific grant agreement 2 (SGA2) of the European quantum flagship project OpenSuperQPlus.
- Cryogenic I/O stabilization with Delft Circuits: Flux-line noise was identified as a dominant source of residual excitation and mitigated through filtering and cabling improvements. This restored stable T₂ erformance and enabled reproducible CZ operation at sweetspot, de-risking scaling.
- Public release of Spin-2+, Starmon-7, Tuna-5 and Tuna-9 quantum computing systems via the Quantum Inspire platform.
- Public dashboards to monitor live system availability and key performance metric


Demonstration of phase-flip error correction with semiconductor spin qubits, implemented in a 2x2 germanium qubit array. The algorithm is sketched in the cartoon and the graph shows the experimental results, demonstrating a finite region where single-qubit phase errors are corrected.

Image of the six-qubit quantum processor described in this article (Nature). The qubits are created by tuning the voltage on the red, blue, and green wires on the chip. The structures called SD1 and SD2 are extremely sensitive electric field sensors, which can even detect the charge of a single electron. These sensors together with advanced control schemes allowed the researchers to place individual electrons at the locations labeled (1)-(6), which were then operated as qubits.

